The IBOX6818 development board is designed using Samsung's S5P6818 chip with 64-bit 8-core A53 architecture. It is completely compatible with the S5P4418 chip pin, and the only difference lies in the internal heart-ARM kernel. The table below lists differences of the two chips:

S5P4418 S5P6818 Time to market October 2014 2014 Technology process 28nm 28nm CPU clock speed 1.4G 1.4G+ Package dimensions 0.65mm pin spacing, 17*17mm2 513-FCBGA package 0.65mm pin spacing, 17*17mm2 513-FCBGA package CPU architecture Cortex-A9 quad-core Cortex-A53 octa-core Cache capacity 32KB*4 I/D cache, 1MB L2 cache 32KB*4 I/D cache, 1MB L2 cache DDR3 interface Single-channel 32-bit data bus, with the operating frequency as high as 800MHz Single-channel 32-bit data bus, with the operating frequency as high as 800MHz Multimedia decoding H.263, H.264, MPEG1, MPEG2, MPEG4, VC1, VP8, Theora, AVS, RV8/9/10, MJPEG (almost all the formats) H.263, H.264, MPEG1, MPEG2, MPEG4, VC1, VP8, Theora, AVS, RV8/9/10, MJPEG (almost all the formats) Multimedia coding H.263, H.264, MPEG4, MJPEG H.263, H.264, MPEG4, MJPEG Display interface RGB, MIPI, LVDS RGB, MIPI, LVDS Maximum display resolution 2048*1280 2048*1280 Ethernet Interface Integrated Gigabit Ethernet controller Integrated Gigabit Ethernet controller GPIO level 3.3V 3.3V ADC 8-channel 12 bit 0~1.8V 8-channel 12 bit 0~1.8V USB interface 1-channel HOST, 1-channel HSIC, 1-channel OTG 1-channel HOST, 1-channel HSIC, 1-channel OTG Chip ID Supporting the unique 128BIT ID Supporting the unique 128BIT ID

The IBOX6818 development board is designed using Samsung's S5P6818 chip with 64-bit 8-core A53 architecture. It is completely compatible with the S5P4418 chip pin, and the only difference lies in the internal heart-ARM kernel. The table below lists differences of the two chips:

S5P4418 S5P6818 Time to market October 2014 2014 Technology process 28nm 28nm CPU clock speed 1.4G 1.4G+ Package dimensions 0.65mm pin spacing, 17*17mm2 513-FCBGA package 0.65mm pin spacing, 17*17mm2 513-FCBGA package CPU architecture Cortex-A9 quad-core Cortex-A53 octa-core Cache capacity 32KB*4 I/D cache, 1MB L2 cache 32KB*4 I/D cache, 1MB L2 cache DDR3 interface Single-channel 32-bit data bus, with the operating frequency as high as 800MHz Single-channel 32-bit data bus, with the operating frequency as high as 800MHz Multimedia decoding H.263, H.264, MPEG1, MPEG2, MPEG4, VC1, VP8, Theora, AVS, RV8/9/10, MJPEG (almost all the formats) H.263, H.264, MPEG1, MPEG2, MPEG4, VC1, VP8, Theora, AVS, RV8/9/10, MJPEG (almost all the formats) Multimedia coding H.263, H.264, MPEG4, MJPEG H.263, H.264, MPEG4, MJPEG Display interface RGB, MIPI, LVDS RGB, MIPI, LVDS Maximum display resolution 2048*1280 2048*1280 Ethernet Interface Integrated Gigabit Ethernet controller Integrated Gigabit Ethernet controller GPIO level 3.3V 3.3V ADC 8-channel 12 bit 0~1.8V 8-channel 12 bit 0~1.8V USB interface 1-channel HOST, 1-channel HSIC, 1-channel OTG 1-channel HOST, 1-channel HSIC, 1-channel OTG Chip ID Supporting the unique 128BIT ID Supporting the unique 128BIT ID